| 摘要 |
PURPOSE:To make a high-speed microprogram control possible independently of the access time of a memory by generating a program so that upper bits of address is not changed. CONSTITUTION:If a sequencer 10 branches in the third cycle to designate an address kn+1 (knot equal to j), an output signal S106 of a comparing circuit 23 becomes ''0'' because upper bits of address in the second cycle which is held newly by an FF group 11, namely, a signal group S101 is different from upper bits A100 of the sequencer 10. Required microprogram information is stored in a memory 12-2. Since the address is changed from (j) to (k), the access time peculiar to memory elements is required for obtaining required information on a signal line 102-2. When a clock signal S116 is changed from ''1'' to ''0'', an FF16 is triggered. Since the signal line S106 is logical 0, the latter half of the third cycle is extended similarly to that of the first cycle.
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