发明名称 PARITY ERROR DETECTING SYSTEM
摘要 PURPOSE:To eliminate an influence caused by a delay of a parity check by executing a parity check instruction provided on a microprogram by other machine cycle than that of other instruction. CONSTITUTION:When executing a parity check, a data having a parity is inputted to a register A10 by an input instruction to a register A8 and an operand indication, and subsequently, a data having a parity is inputted to a register B11 by an input instruction to the register 11 and an operand indication. Thereafter, a parity check instruction is issued, and in an operand field, a parity check is indicated with regard to both the registers A10, B11, by which the parity check can be executed at the same time with regard to both registers.
申请公布号 JPS60134346(A) 申请公布日期 1985.07.17
申请号 JP19830239766 申请日期 1983.12.21
申请人 HITACHI SEISAKUSHO KK 发明人 YANO JIYUNICHI
分类号 G06F9/22;G06F9/02;G06F11/10 主分类号 G06F9/22
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