发明名称 VECTOR ARITHMETIC DEVICE
摘要 PURPOSE:To obtain the high-speed primary cyclic operation which executes multiplication by setting the addition results as the multiplicand by making a normalization circuit operate independently. CONSTITUTION:A datum b1 which is normalized by a normalization circuit 15 is selected by a multiplier register 16 and a datum a1 is selected by a control circuit. After they are stored in a multiplicand register 17, they are inputed in a multiplier 18. After the multiplier executes the multiplication and the multiplication results are stored in a multiplication result register 19, the data are transferred to an augend register. The data which are stored in an addend register and the augend register are inputted to an adder 22, and addition is executed. The data which are stored in a result store register 24 are stored in a main storage device 11 by a control circuit 30, and the data which are stored in the multiplicand register 17 are used as the multiplicand of the next element.
申请公布号 JPS60134379(A) 申请公布日期 1985.07.17
申请号 JP19830241920 申请日期 1983.12.23
申请人 HITACHI SEISAKUSHO KK 发明人 FURUKAWA MASAO;NAKANO HIROSHI
分类号 G06F17/16;G06F15/78 主分类号 G06F17/16
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