| 摘要 |
PURPOSE:To improve the signal conversion processing efficiency by adding a comparator including a gate circuit and a selector or the like to a signal converter so as to decrease the signal conversion processing time and attaining high speed processing. CONSTITUTION:An offset value is added to a data to be converted at an adder 1B of a digital converter, the result of addition is selected by the 1st selector 2B and the output of the 2nd selector 7B is selected at the 2nd and succeeding steps. The output of the selector 2B and the data value stored in ROMs 9B, 10B are compared by comparators 3B, 4B, the outputs of the comparators 3B, 4B are fed to a gate circuit 8B so as to output the conversion data in 2-bit depending on the input state. Moreover, the values of ROMs 11B, 12B are subtracted at subtractors 5A, 6B from the output value of the selector 2B, their outputs are fed to the selector 7B, the result of subtraction or the output of the selector 2B is selected depending on the input state. The signal processing time is decreased by the control of the control circuit 14B so as to improve the signal processing efficiency. |
