发明名称 METHOD OF MAKING PLANARIZED JOSEPHSON JUNCTION DEVICES
摘要 <p>The present invention teaches a method of planarizing built-up vacuum deposited surfaces or areas on Josephson junction and semiconductor devices so that successively deposited layers do not replicate the undulations of previous layers. After a surface layer is deposited in a vacuum system and part of the surface is etched, a raised surface is generated. A photoresist lift-off stencil is applied to the surface to be preserved and the material to be removed is removed by isotropically etching so as to leave an overhang or ledge of photoresist material over the area of the material retained. A new layer of material is now deposited by vacuum deposition so as to almost fil the area to be planarized. A small gap remains between the top of the new material being vacuum deposited and the bottom of the photoresist stencil so that solvent can be introduced to the stencil. When the photoresist stencil is removed, the top of surface being preserved is substantially planar with the new layer of material.</p>
申请公布号 CA1190648(A) 申请公布日期 1985.07.16
申请号 CA19830423724 申请日期 1983.03.16
申请人 SPERRY CORPORATION 发明人 YOUNG, PETER L.;STEIN, BARRY F.;SHEPPARD, JOHN E.
分类号 H01L39/24;(IPC1-7):G11C11/44 主分类号 H01L39/24
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