| 摘要 |
PURPOSE:To prevent malfunction at the time of reading operation when respective transistors (TRs) used have the same size by applying clocks having reverse phases each other to respective transmission gates connected to a data line. CONSTITUTION:Respective one-ends of the transmission gates (TMGs) 81, 82 each of which consists of an MOSFET switch are connected to the data line 80, a CMOS type inverter 83 is connected between the other terminals of the TMGs 81, 82 and a C<2>MOS type inverter 84 is connected like a ring between the input and output terminals of the inverter 83. The TMG 81 and the inverter 84 are driven by clocks phi1, phi2 having reverse phases each other. At the writing mode, the TMG 81 is opened while closing the TMG 82 for a fixed period, and the inverter 84 is made non-operation state. At the reading mode, the TMG 82 is opened only for a fixed period while closing the TMG 81 as it is. |
