| 摘要 |
PURPOSE:To eliminate the charge distribution due to floating capacitance by adding a load element to an (n+2) multi-input CMOS gate circuit having less number of component elements. CONSTITUTION:The load element QL2 is connected between the connecting point of the 1st power supply VSS and the 2nd power supply VSS. In this circuit the level of a1-a4 is all at L during the period 0-1, only a P-channel transistor (TR) QP1 is turned on and QN1-QN4 are all turned off. Thus, an electric charge is charged to a C1 by the QP1, while an electric charge is charged to the 2nd load element QL2 being comparatively low in the resistance to a C2. When the charging is finished in the period of 0-1, the C2 is charged up to a VDD level. Thus, the a1 goes to H at the next period 1-2 and no charge distribution from the C1 to the C2 when the QN1 is turned on takes place. The operation is similar in other periods. |
