发明名称 MULTIPLIER AND DIVIDER
摘要 PURPOSE:To obtain a multiplier and divider for executing a division without deteriorating its accuracy by executing a multiplication of an effective numerical bit of a reciprocal of a divisor and a dividend, and executing a shift of the corresponding quantity. CONSTITUTION:In case of executing a division, a dividend V and a reciprocal of a divisor D read out of a storage device 702 from a switching circuit 705 are inputted to a multiplier 701, a shift quantity read out of the storage device 702 from a controlling circuit 706 is inputted to a shifting circuit 707, a result of multiplication of the multiplier 701 is shifted by the shifting circuit 707, and the quotient Q is obtained. The reciprocal of the divisor and the shift quantity are written in the storage device 702. That is to say, the divisor D is shown by a binary number and a decimal number, also the reciprocal of the divisor D is shown by a binary number, and this effective numerical bit is written as a storage data in a reciprocal part 703 of the storage device 702. The shift quantity is used for correcting a digit shift generated in order to set a storage data to a desired effective numerical bit, and in accordance with this shift quantity, an output of the multiplier 701 is shifted by the shifting circuit 707, and the digit matching is executed.
申请公布号 JPS60129834(A) 申请公布日期 1985.07.11
申请号 JP19830239104 申请日期 1983.12.19
申请人 MATSUSHITA DENKI SANGYO KK 发明人 MORI TOSHIKI;AONO KUNITOSHI;HASEGAWA KENICHI;YAMADA HARUYASU
分类号 G06F7/52;G06F7/487;G06F7/53;G06F7/535;G06F7/537;G06T5/20 主分类号 G06F7/52
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