| 摘要 |
PURPOSE:To execute a parallel processing having no parallel processing obstructing factor caused by reusing a register by plural instructions, by providing physical registers of about N pieces in order to set the maximum number of instructions processed simultaneously in a system, to N. CONSTITUTION:In a cycle C3, a load instruction LD is set to an instruction register and an operator E2 is started. In order that a floating point register ''0'' address FR0 to be stored is made to correspond again physically to other register FR0' by the instruction LD, the LD instruction executes the processing immediately in the C3 and stores its result. That is to say, the LD instruction takes sole posession of the E2 only in the C3, and in C4, the E2 can receive an operation of the following instruction. Subsequently, when an adding instruction AD is set to the instruction register in the C4, the operator E2 is started, a result of the LD instruction is read out of the register FR0', the operation is started from the C4 and ended in C5, and its result is stored in the FR0'. In this way, two instruction processings of MD, STD and LD, AD can be executed in parallel by plural operators. |
