| 摘要 |
PURPOSE:To make it possible that a CPU which controls an address bus of x- number of bits accesses an address space of m-number of bits (m>x), by providing address banks having extended addresses and an address bank selecting decoder. CONSTITUTION:A CPU10 can access directly address information consisting of x- number of bits and is connected to address banks 14-1-14-n' through an address bank selecting decoder 15. Banks 14-1-14-n' have extended addresses y1-yn' including upper n-number of bits of address information, and the decoder 15 outputs selecting signals a-1-a-n'. That is, the decoder 15 assignes upper n-number of bits of the CPU10 to address bank selecting bits and decodes upper n-number of bits on an address bus 12 and selects address banks and outputs their contents. Thus, the extended address of y-number of bits including upper n-number of bits is set to each address bank, and the CPU10 which controls the address bus of x-number of bits can access the address space of m-number of bits (m> x). |
