| 摘要 |
PURPOSE:To execute an operation in one instruction at different time respectively time by providing two instruction registers, and connecting them independently to a address generating device for data and a data processing device, respectively. CONSTITUTION:An address is given to a memory 8 for instruction by an address generating device 7 for instruction, and its read-out instruction is inputted to the first instruction register 9. At the same time, the contents of the first instruction register 9 are transferred to the second instruction register 10. The contents of the first instruction register 9 are applied to an address generating device 11 for data. Also, the contents of the second instruction register 10 are applied to a data processing device 13. The address generating device 11 for data applies an address to a memory 12 for data, and the data processing device 13 executes write and read-out of a data to its selected memory. The timing is one machine cycle for fetching an instruction, and in the next cycle, an access and decode of the memory for data are executed, and the data processing is executed by the third machine cycle.
|
