发明名称 CONTROLLING SYSTEM OF HIT RATE MEASUREMENT
摘要 PURPOSE:To measure a hit rate of a buffer storage automatically at a prescribed period by providing a data processing device with a hit rate measurer, a timer, and a delay circuit. CONSTITUTION:A timer 21 outputs a signal once every several 10ms, and the output signal is inputted to a hit rate measurer 23, which measures the hit rate of a buffer storage 20, and a delay circuit 22. The signal inputted to the measurer 23 starts the measurer 23, and the signal inputted to the circuit 22 is delayed by a prescribed delay time. This delayed signal is not only a stop signal of the measurer 23 but also an external interrupt signal of a processing part 24. Consequently, the measurer 23 is started simultaneously with output of the timer 21 and is stopped after the delay time. This state is repeated at the period of the timer 21, and the measurer 23 inputs the hit rate during operation to a main storage device 1. The hit rate measurer 23 and etc. are provided in this manner to measure the hit rate of the buffer storage automatically at a prescirbed period.
申请公布号 JPS60129857(A) 申请公布日期 1985.07.11
申请号 JP19830238622 申请日期 1983.12.16
申请人 FUJITSU KK 发明人 MURAMATSU HIROSHI;EBINE HIDEAKI
分类号 G06F12/08;(IPC1-7):G06F12/08 主分类号 G06F12/08
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