发明名称 ARITHMETIC DEVICE
摘要 PURPOSE:To round an error generated at the time of shifting to the minimum by adding a value of the most significant bit overflowing at lower-order at the time of a right shift, to a shifted result, and inputting ''10''...''0'' from the least significant bit at the time of a left shift. CONSTITUTION:An adder and subtracter 5 outputs an input A+ an input B+ a carry-in (b) at the time of an addition mode, and outputs the input A- the input B- the carry-in at the time of a subtraction mode, in an adder 3. An accumulator 6 is connected to an output of the adder and subtracter 5, and also becomes an input of the adder and subtracter 5. (a) and (b) being output values of a barrel shifter are inputted to the input B and the carry-in of the adder and subtracter 5, respectively. Also, by a function of the adder and subtracter 5, the input A+(a+b) and the input A-(a+b) are obtained at the time of the addition mode and at the time of the subtraction mode respectively, therefore, the round- off (a)+(b) of a shifter can be buried into the adder and subtracter under the shifter even if an adder for round-off is not added especially.
申请公布号 JPS60129832(A) 申请公布日期 1985.07.11
申请号 JP19830239148 申请日期 1983.12.19
申请人 MATSUSHITA DENKI SANGYO KK 发明人 KUROSAKI NATSUME;UEDA KATSUHIKO
分类号 G06F7/00;G06F5/01;G06F7/38;G06F7/76 主分类号 G06F7/00
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