| 摘要 |
PURPOSE:To obtain a decoder of a double error correcting three bit error detecting BCH code by adding an error decision circuit to a double error correcting BCH code decoder. CONSTITUTION:An error decision expression is made Z=S0(S1<3>+S3), and at the time of Z=0, Znot equal to 0, and S0=S1=S3=0, they are decided to be a double error or below, a triple error, and no error, respectively. In case of the double error, S1 and S3 are changed to an exponential expression by an ROM1, S1<3> is obtained by an AD3, and error positions X1, X2 are obtained through an ROM6 and an AD7. Subsequently, in case of a triple error, Znot equal to 0, and an error is detected. In case of S1<3>+S3not equal to 0, an output of an OR12 becomes ''1'', and since S0=1, an output of an AND13 is ''1''. Next, when it is decided to be a double error, the ROM (y2)6 outputs all ''1'', therefore, an output of an AND14 becomes ''1'' and an error is detected. Also, even in case of S1=0 or S3=0, an error is detected, and in case of S0=S1=S3=0, an AND11 becomes ''1'', and there is no error. |
