| 摘要 |
PURPOSE:To set generation of a halting signal, an interrupting signal, etc. to plural address parts by providing a control information area, setting the control information, and detecting a fact that an optional address is being executed. CONSTITUTION:A decoder 51 of a control part 39 is an address decoder which is common to a main storage area 37, and when address information (k) to which the area 37 is allocated is inputted, a decoding signal (m) which becomes a selecting signal of the main storage area 37 is outputted. A gate circuit 52 makes a Write executing signal (r) active and outputs it, when the decoding signal (m) is active, also a Read/Write signal (j) is H (Write), and also control information (n) is active. When this signal is used as a stop signal of a chip 32 to be inspected, in case it is desired to Write an address by which a bit ''0'' of the control information is set to ''1'', the execution of the chip 32 to be inspected can be halted. In the same way, by the control information, a halting signal (s), an interrupting signal (t) and a preliminary signal (u) are outputted from gate circuits 53, 54 and 55. |
