| 摘要 |
PURPOSE:To decrease the amount of hardware and also to attain miniaturization by constituting a delay realizing circuit section of a transmission delay simulator of an RAM and its address control circuit. CONSTITUTION:In realizing a delay for, e.g., 8XN bits' share, a reception data RD is converted into an 8-bit parallel data and the result is written in the RAM9. When an address bus BA being an output of a decrement counter 10 with preset represents an address K, the data written precedingly in the address K of the RAM9 is read by the 1st half of a clock WR of an 8-bit period and the present data is written at the latter half. Then the address is counted down by the clock WR, the said write/read is repeated and when the address reaches ''0'', an N set to a DIP switch is loaded to the counter 10. Furthermore, write/ read is repeated and when the address reaches K, the data written when the preceding address was K is transmitted to a transmission shift register 4. |
