| 摘要 |
PURPOSE:To attain high-speed processing by storing data changed by a preceding instruction for the operand of the next instruction and taking it over to the succeeding instruction while being matched at start of operation of the next instruction. CONSTITUTION:When a decimal instruction code is set to an instruction register 10, the content of a base register represented in B1, B2 from a conventional register 12 as the operation of D stage is read to lines 12A, 12B, the operation of (B1)+D1, (B2)+D2 is performed by displacements D1, D2 at adders 14, 15, the result is set to logical address registers 16, 17, and length codes L1, L2 are set to registers 18, 19 via lines 10C, 10D. An operand code OP is set to a register 13 via a line 10E. Moreover, the content of an instruction register 10 is fed to an OSC (operand store compare) control circuit 11.
|
