| 摘要 |
A variable radix processor is constructed on 1.25 micrometer CMOS/SOS. The processor, based upon a predetermined algorithm, is constructed to process radix 2 to 7 data wherein the data is input in a parallel-by-word, parallel-by-bit format. A format selection switch has the data input whereafter a plurality of switches outputs an address format to a bit-slice multiply-adder. The bit slice multiply-adder has ROMs addressed by the format selection switch. Based upon the predetermined algorithm, each unique address format causes the ROMs to output a unique word in parallel bits to a tally cascade circuit and then to a fast-carry adder. The processor can operate on a transfer function such as ZA=+/-(A+/-C), ZB=B where A= SIGMA aiXi, B=biXi with very high throughput rates such as 380 million operations per second.
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