DECISION CIRCUIT OF ODD/EVEN FIELD

摘要

PURPOSE:To obtain high aging changes and stable actions by delaying a horizontal synchronizing signal digitally through the use of a PLL circuit and a shift registor. CONSTITUTION:One of horizontal synchronizing sigals inputted from a terminal 8 is inputted to a PLL circuit 10 and a frequency signal 16fH 16 times said signal is made from the signal. The other of the horizontal synchronizing signals is inputted to a shift registor 12 of an odd/even field discrimination device 11, and said 16fH is outputted as a clock signal by delaying the inputted horizontal synchronizing signal by 24mus with respect to a vertical synchronizing signal. This is called an H' synchronizing signal. Then a vertical synchronizing signal of a terminal 9 and the H' synchronizing signal are inputted to a clock input terminal of a D type flip-flop 13 and a data input terminal, respectively, and an odd/even field decision signal is generated.