发明名称 VERTICAL DEFLECTION CIRCUIT
摘要 PURPOSE:To attain ease of design of stabilization of a bias point of a vertical output amplifier and design of the correction of vertical linearity by disconnecting completely a DC feedback circuit and an AC feedback circuit. CONSTITUTION:An adder circuit 21 is provided between a drive amplifier 2 and a vertical output amplifier 3. Then a parabola form voltage VP obtained at a connecting point P1 is fed to a sample and hold circuit 22, the voltage VP is sampled by a sampling pulse SP obtained at a point of time delayed by a fixed time from a vertical synchronous pulse position and its sampling value is held. The hold voltage is fed to the adder circuit 21 via an LPF23 to form a DC feedback loop thereby stabilizing the bias point of the amplifier 3. Moreover, an AC component obtained at a connecting point P2 is fed to other input of the drive amplifier 2 to form the AC feedback loop thereby correcting the vertical linearity.
申请公布号 JPS60127877(A) 申请公布日期 1985.07.08
申请号 JP19830236785 申请日期 1983.12.15
申请人 SONY KK 发明人 KIKUCHI MASABUMI;ISHIHATA KIYOSHI
分类号 H04N3/16;H04N3/23 主分类号 H04N3/16
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