| 摘要 |
PURPOSE:To reduce the probability of mis-reception by obtaining a value in following to the majority decision logic from plural data obtained through the use of plural detecting clock ulses as a detection output during the period when the same detected result is obtained in one bit of data. CONSTITUTION:A detected data is stored in flip-flops 1, 2 by detecting clock pulses phi1, phi2 at the first half of a bit data section (a). Since the data is stored in a 3D flip-flop 8 by a detection clock pulse, the detected output S is ''0'' at the end of first half of the bit data section (a) and the detected output K goes to ''1'' at the end of the latter half and the information of the bit data section (a) is discriminated as ''1''. An output E of a flip-flop 11 goes to ''0'' at the end of the bit data section and the information is detected without error. When a positive noise N2 is mixed in the bit data section (c), the noise width is narrow comparatively and the level corresponding to 3 detection pulses phi4-phi6 is low level to the two detection pulses, then the end part K of the final detecting output S goes to a high level and no erroneous operation occurs. |
