| 摘要 |
PURPOSE:To shorten load resistance length by applying voltage between a polycrystalline silicon pattern and a conductive layer opposed through a dielectric film, forming a channel in said pattern and lowering the resistance of a part of the pattern. CONSTITUTION:Gage electrodes G1-G4 are formed to the lower section of a VCC wiring through a dielectric film while a conductive layer parttern EL consisting of first layer polycrystalline Si layer (Poly A) in the same layer as the gate electrodes, to which an N type impurity is introduced in high concentration and resistance thereof is lowered, is formed. Positive high voltage is applied between the EL and the VCC wiring. Accordingly, carriers in Poly B are stored in a region in the vicinity of a dielectric film, an Si3N4 film 25, shaped between the EL and the VCC wiring in the VCC wiring formed by Poly B, to which the impurity is not doped or which has high sheet resistance, and a channel having low sheet resistance is formed. |
