发明名称 GATE ARRAY
摘要 PURPOSE:To prevent the characteristics failure that is caused by a bonding pad contacting to an adjacent bonding wire or chip, by making the space between the bonding pads at the corners of a semiconductor substrate larger than that at the central part of the semiconductor substrate. CONSTITUTION:The bonding pads BPA1, BPA2, BPA3, BPA4, BPA etc. on the I/O cell C1/0, which are connected to the internal leads of a package, facing to the four corners of the chip 1 including the place on the four corners on the semiconductor chip 1 where is normally left empty, are arranged with the larger space D2 than the space D1 for the normal bonding pads BPB1, BPB2, BPB etc. With the arrangement mentioned above, the space DA of the bonding wire BWA, which connects an internal wire of the package positioned on the region facing to the four corners of the chip 1 to a bonding pad, is substantially widened, thereby reducing the probability of bonding wires contacting each other due to the deformation of the wires.
申请公布号 JPS61194863(A) 申请公布日期 1986.08.29
申请号 JP19850035472 申请日期 1985.02.25
申请人 FUJITSU LTD 发明人 YAMASHITA KOICHI;FUJII SHIGERU
分类号 H01L27/118;H01L21/60;H01L21/82;H01L23/485 主分类号 H01L27/118
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