| 摘要 |
PURPOSE:To reduce the size of a programmable logical array sufficiently and speed up logical operation. CONSTITUTION:Logical elements are coupled with signal lines L11-L1l1, L21- L2l2...Lk1-Lklk and specific product term lines among P1-Pw, and a specific coupling pattern is formed by them. When logical signals are inputted from input lines I1-In, they are ANDed according to said coupling pattern to obtain their logical output signals on the product term lines P1-Pw. Those obtained logical output signals and ORed according to the coupling pattern formed by coupling logical element with specific signal lines among specific signal lines M11-M1m1, M21-M2m2...Mt1-Mtmt among signal lines M1-Mt and specific product term lines among P1-Pw. Then, their logical output signals are outputted through output lines O1-Om. |
