| 摘要 |
PURPOSE:To maintain the coincidence of an address registered in a CPU and a storage controller by providing a buffer storage device storing an instruction data and an address of operand data in a main storage device to the CPU. CONSTITUTION:CPU0-3 are provided with a buffer storage device (cache memory) storing the instruction data IF and an address of the operand data OP in the main storage deice MSU. When the CPU1 extracts the IF data corresponding to an address A of the MSU from the MSU, the IF data and the address of the IF data in the MSU are written and also the address A and an identifier of the address A representing the IF side description of a buffer address array are transferred to a storage controller MCU. When the CPU2 writes an OP data to an address B of the MSU, the identifier where the address represents the OP side description of the cache memory is transferred similarly. Thus, the coincidence of the address registered in the CPU and MCU is maintained without increasing the number of interfaces.
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