发明名称 |
SUPER-IMPOSE CONTROL CIRCUIT |
摘要 |
PURPOSE:To improve the efficiency of access from a CPU to a storage part storing character pattern information to be displayed on a display device by forming a CPU timing generating part and a display timing generating part independently. CONSTITUTION:When the CPU2 is to write or read out data in/from the storage part 1, a signal generated by a CPU timing generating part 6 is used. Even if a display control part 3 has completed display and stopped the operation of a display timing generating part 7, the CPU timing generating part 6 holds the operating state as it is. When an external cynchronizing signal is inputted and the display timing generating part 7 starts the operation again, the CPU timing generating part 6 temporally stops by a signal from a timing generating part 5 and then starts to operate instantaneously and synchronously with the display timing generating part 7. Consequently, the CPU can write or read out data in/ from the data storage part efficiently almost without waiting time.
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申请公布号 |
JPS60124182(A) |
申请公布日期 |
1985.07.03 |
申请号 |
JP19830232399 |
申请日期 |
1983.12.08 |
申请人 |
MATSUSHITA DENKI SANGYO KK |
发明人 |
SUGITA TAKUYA;NAKAMATSU TOSHIAKI;WADA RIYOUICHI |
分类号 |
G09G1/00;G09G5/32;H04N5/445 |
主分类号 |
G09G1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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