| 摘要 |
<p>PURPOSE:To prevent deterioration of performance characteristics and to improve a poor yield by a method wherein the short side and the long side of a rectangular semiconductor device run parallel with specified orientations and the nest of such lattice defects as slips overlaps the useless region of a wafer. CONSTITUTION:The long side or the short side of a CCD line sensor 211-21n, 221-22n is arranged to be in parallel with an orientation (010) and the other side in parallel with an orientation (001), whereafter a pattern is drawn on the primary plane (100) of an Si wafer 1, an integrated circuit is formed, and then the Si wafer 1 is divided into chips. In this method, a region a1-a4 is located on the useless region (whereon no chips are formed) of the Si wafer 1. An orientation flat 3 is positioned on a plane (011) prone to cleavage.</p> |
