| 摘要 |
PURPOSE:To form a capacitive element with large capacity without enlarging the size of a chip, by a method wherein a capacitive element is formed on an element formed in a semiconductor substrate, with the first and second metallic film patterns and the insulating film between them constituting a capacitive element. CONSTITUTION:On the surface layer of a P-type silicon substrate 11, an N<+> type diffusion wiring layer 12 to supply the power source electric potential to the element not shown in the Figure. The surface of the substrate 11 is coated with a silicon oxide film 13 on which a power source wiring layer 14 is formed. The wiring layer 14 is ohmically contacted to the diffusion wiring layer 12 through a contact hole. Further, a capacitor electrode 16 is formed on the wiring layer 14 through a CVD-SiO2 film 15. With this construction, the power source wiring layer 14, the CVD-SiO2 film 15, and the capacitor electrode 16 form a capacitive element. |
