| 摘要 |
<p>A complementary MOS static EXCLUSIVE OR gate is formed by a PMOS logic network having a pair of cross-coupled PMOS transistors (M5, M6) and an NMOS logic network having two parallel branches, each of the branches containing a separate pair (M1, M2 and M3, M4) of NMOS transistors connected in series. The arrangement prevents coupling or "conflict" of the signal (A) on one of the gate input terminals (25.5) to the signal (B) on the other of the input terminals (26.5) as is possible in prior art similar logic gate arrangements.</p> |
