Improvements relating to electrical circuits for timing signals.

摘要

A counter 47 is provided to count an expected 32 pulses in a pulse train comprising a signal received at A and passing through an AND gate 60 when enabled. However if the pulses in the leading and trailing edges are of low amplitude they may be below a threshold level and thus be missed so that the counter 47 will not reach the required count of 32. However when the sequence of pulses terminates a counter 62 is then able to reach a full count of three upon receipt of pulses from an oscillator 64 transmitted at twice the frequency of the pulses in the signal. This releases a latch 58 so that the oscillator pulses can pass through the AND gate 65 to the counter 47 so that the count is completed. Since the losses of pulses at the beginning and end of the signal are expected to be symmetrical addition of pulses at twice the frequency in the counter 47 to those already received from a signal will compensate for the pulses lost at the beginning and end of the signal and will ensure that the output from the counter 47 occurs approximately at the same instant when the end of the trailing edge of the signal is reached. Hence the output from the counter 47 is a true reflection of the timing of receipt of the signal.