| 摘要 |
PURPOSE:To save the amount of hardware by adopting the constitution that an optionally determined pattern is subjected to scan-in and a value as the result of logical operation of outputs of plural logical elements is displayed at a scan address. CONSTITUTION:The scan-in of 0, 1 is attained by simply giving the scan address of two SCAN ADDRESSes 1 and 0 to a latch number mutual exclusive condition. Each one scan address is assigned respectively to three latches, for example, and when the OR logical value of the three latch outputs is displayed while being scan-out, no scan-out circuit exists in the latches B, C and the value is given to the latch A through output lines 520, 530. The value of the OR logic is subjected to scan-out when the value being the OR logic of the latch state of the latchs A, B and C is inputted to an AND501 by an OR500 in the latch A and a scan address is given to the SCAN ADDRESS 0. |
