发明名称 |
SUPERVISION CONTROLLING SYSTEM OF DATA PROCESSOR |
摘要 |
PURPOSE:To easily perform sure supervision control with a system which monitors the execution of a data processor, by putting output instructions of the 1st and 2nd control signals in a routine to be executed by interruption processing. CONSTITUTION:An interruption signal generated upon receiving an interruption requesting signal IRQ is sent to a processor 3 and a control section 8 stops a currently executed program P and starts a routine R. A statement C which designates the transmission of a clear pulse CL and another statement S which designates the transmission of a strobe signal STB are assembled into the routine R. A clear signal CL is outputted at a time t3 by means of the statement C. A signal generating section 7 is reset at the time t3 by the signal CL. When the processor 3 executes the statement S, a pulse generating section 4 is started and the strobe signal STB is outputted at a time t4. |
申请公布号 |
JPS60123939(A) |
申请公布日期 |
1985.07.02 |
申请号 |
JP19830231820 |
申请日期 |
1983.12.08 |
申请人 |
FUJITSU KK |
发明人 |
AMARI HIDETOSHI;YAMAZAKI KIYOHIRO;YOSHIMURA KAZUHISA |
分类号 |
G06F11/30;(IPC1-7):G06F11/30 |
主分类号 |
G06F11/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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