发明名称 SYSTEM FOR CONTROLLING BUFFER STORAGE
摘要 PURPOSE:To reflect an operand store in an instruction fetch buffer storage without requiring synchronism between both pipelines of operand fetch and instruction fetch, by performing the above-mentioned reflection by utilizing the address and data of a store buffer. CONSTITUTION:By utilizing the address and data of a store buffer (STB) 10 installed to a store through type buffer storage, an operand store is reflected in an instruction fetch buffer storage. A store address set in a store address register (STAR) 9 is checked whether or not a relevant address exists in an instruction fetch buffer storage 5 before the address is sent to a main storage. When the revelant address exists, store data in the STB10 is written through an instruction store data register (ISDR) 8. Therefore, the store access of an operand is not necessarily made by synchronizing both pipelines of operand fetch and instruction fetch to each other.
申请公布号 JPS60123936(A) 申请公布日期 1985.07.02
申请号 JP19830231104 申请日期 1983.12.07
申请人 FUJITSU KK 发明人 TONE HIROSADA
分类号 G06F9/38;G06F12/08 主分类号 G06F9/38
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