发明名称 DUPLEX RAM SURFACE CHANGE-OVER TIMING SYSTEM
摘要 <p>PURPOSE:To decrease the hard quantity by setting the initial phase of satellite side data to the input side of a duplex RAM surface change-over circuit so that data dead zones at the satellite side and the ground side are coincident and providing an initial phase setting part which generates a surface change-over signal almost in the central part of the basic frame on the basis of the initial phase. CONSTITUTION:Satellite side data are a period 100mus on the basis of a satellite side clock C1, and on the other hand, ground side data are 2ms on the basis of the ground side clock C2. A counter 5a starts to measure from a frame timing FT by a satellite side clock C1, generates the surface change-over timing signal S after 1ms, makes the symbol S coincident to ground side data dead zones and sends a JK flip flop 3. The surface change-over timing is set to the center of the basic frame. Consequently, a frequency deflection quantity by Doppler effects of the satellite side data can be absorbed from -900mus to +1ms on the basis of the change-over timing signal S.</p>
申请公布号 JPS61196636(A) 申请公布日期 1986.08.30
申请号 JP19850035269 申请日期 1985.02.26
申请人 FUJITSU LTD 发明人 YAMAGUCHI SEIICHI
分类号 H04J3/06;H04B7/155;H04L7/00 主分类号 H04J3/06
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