发明名称 SPLIT AND PARALLEL PROCESS PROGRAMMABLE CONTROLLER
摘要 PURPOSE:To process a program ladder at a high speed by writing the program ladder in the program memory of each CPU after splitting the program ladder and, at the same time, a coil signal output in a common RAM. CONSTITUTION:A multi-CPU system is formed with CPUs 1, program memories 2, internal RAMs 3 of working areas, a common RAM7, bus buffers 4 which connect a common bus 6 to a high-rank controller 8, and input-output interface 9 with external apparatuses 10. This program ladder is divided into two areas and written in the program memory 2. When both CPUs 1 are started, they proceed to analyze the above mentioned ladder and write a coil signal obtained as the result of the calculation in the common RAM7. Each CPU1 waits for the next start up when they complete the process of the ladder area and, when the next start up is cammanded, the above mentioned coil signal is transferred to the internal RAM3 as contact information and a series of ladders are analyzed based on the contact information.
申请公布号 JPS60123903(A) 申请公布日期 1985.07.02
申请号 JP19830232101 申请日期 1983.12.07
申请人 YASUKAWA DENKI SEISAKUSHO KK 发明人 HARA KENJI
分类号 G06F15/16;G05B19/05 主分类号 G06F15/16
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