| 摘要 |
PURPOSE:To realize a semiconductor integrated circuit in a CMOS structure, wherein a freedom degree in design has been enhanced and a large scale integration and a higher- performance actuation have been contrived, by a method wherein a fundamental cell is used as a symmetrical pattern in between mutually adjacent cell rows, the cell rows are mutually arrayed in close contact, and also, a wiring is arranged on the cell rows in a multilayer structure. CONSTITUTION:A P<+> type layer 34 and an N<+> type layer 36, by both of which a P type well 32 and an N type Si substrate 31 are respectively connected to a power supply line VSS and a power supply line VDD, are provided in the vicinity of the boundary between each element region. By this CMOS structure, when a transistor TN is turned to ON, collector current runs through the N type Si substrate 31, but this current is supplied from the N<+> type layer 36. Accordingly, voltage drop due to a resistor RN is less and forward bias, which is impressed on a transistor TP, is less, while when the transistor TP is turned to On, current runs through the P type well 32, but the current is absorbed in the P<+> type layer 34, the voltage drop at a resistor RP is less and the forward bias, which is impressed on the transistor TN, is less. Accordingly, the positive feedback gain of the parasitic circuit is less. As a result, it becomes difficult for the latch-up phenomenon to generate. |
