| 摘要 |
PURPOSE:To obtain the high degree of integration without requiring a large element isolation region by continuously forming gate conductive layers in a plurality of MOS transistors arranged in series by polysilicon and insulating and isolating gates for the MOS transistors by a high resistance region in response to element isolation regions in each MOS transistor. CONSTITUTION:Source diffusion regions 14a, 14b and drain diffusion regions 15a, 15b are formed in series on the surface of a semiconductor substrate 13. A polysilicon gate 21 is shaped continuously in response to channel regions formed among each region 14a, 14b are region 15a, 15b through gate oxide films 16a, 16b. The polysilicon gate 21 is insulated and isolated electrically by a high- resistance insulating region 25 shaped in response to an element isolation region 24. Accordingly, the width B of the element isolation region can be set in comparatively narrow size only by resolution by a photoetching method, the region of the semiconductor substrate 13 except the element region can be reduced, and the degree of integration of an element can be increased. |
