| 摘要 |
PURPOSE:To reduce the time difference between a positive-phase output and an anti-phase output by connecting capacities among plural nodes of individual clock generating circuits in a clock generating circuit having positive-phase and anti-phase clock generating circuits. CONSTITUTION:Inverters 6, and 8'-10' are cascaded successively to an input clock terminal 1 to form a positive-phase clock output circuit 4. Inverters 6-10 are connected successively to the input terminal 1 to form an anti-phase clock output circuit 5. In the clock generating circuit constituted in this manner, capacities C1-C4 are connected among plural codes N1-N3 and N'1-N'3 of clock output circuits 4 and 5. Thus, the time difference between the output of the positive-phase clock output circuit 4 and the output of the anti-phase clock output circuit is reduced by the bootstrap effect of each capacity C. |
