| 摘要 |
PURPOSE:To reduce reset noises from an FDA for a CCD by minimizing the parasitic capacitance of the FDA. CONSTITUTION:An output terminal from a CCD1 is connected to the first terminal 2A of an output diode 2, and connected to a first power supply 4B by a reset switch 4. The first terminal 2A is connected to a gate for an amplifying MOS transistor 5, a drain for the transistor 5 is connected to a second power supply 5B, and a source 5A for the transistor 5 is connected to a drain for a load transistor 6. An output node 5A for a first step source follower amplifier is connected to a base for the emitter follower transistor 6. A collector for the transistor 6 is connected to a third power supply 6B, and an emitter 6A as an output node is connected to a constant current load 7 manufactured in another chip. Since the N<+> region 2A of the output diode 2 is separated from gate electrodes 1A, 4C and its width is designed in narrow width, the parasitic capacitance of the N<+> region 2A is reduced, and the clock noises of the CCD and the clock noises of the reset switch are also minimized largely. |
