| 摘要 |
PURPOSE:To set three digital states with one input terminal by setting gate widths and gate lengths of the 1st and the 2nd inverters comprising C-MOS transistors (TR) in specific relations. CONSTITUTION:Logical threshold voltages of the inverters V1 and V2 composed of a C-MOSTR are so set that VSS<V1<V2<VDD, where VDD is a source voltage and VSS is an ground voltage. For the purpose, (WN1/LN1)/(WP1/LP1)>(WN2/ LN2)/(WP2/LP2), where WN1 and WP1, and WN2 and WP2 are gate widths of MOSTRs of an N channel CH and a PCH of the INV3 and INV4 and LN1 and LP1, and LN2 and LP2 are gate lengths. Further, the input level VIN at the common input terminal IN3 of the INV1 and INV2 is so set in states A, B, and C that VIN<V1, V1<VIN<V2, and V2<VIN, and consequently terminals OUT3 and OUT4 outputs 1, 0, and 0, and 1, 1, and 0 respective according to the respective states. |
