| 摘要 |
PURPOSE:To shorten an access time when an address continues by detecting the coincidence of the contents between a stop address register, and an increment or a decrement, and by providing a coincidence circuit which inhibits the increment or the decrement. CONSTITUTION:When reading is executed continuously, a final address is written in a stop address register 9 from an outer input data line 11. Next, the first address is inputted from an outer address line 1, and data of a memory cell group 4 are stored in an output data register 7. An RD input 12 is activated, and it is outputted to an outer data line 5. At the same time when the RD input 12 is not activated, an increment 8 operates, and it changes the contents of an address register 2. Thus, the sequence addresses are incremented by the RD input 12. When the final address is written in the address register 2, the data are stored in the register 7, and at the same time, a coincidence circuit 10 detects the coincidence with the stop address which is written in the register 9. Then, the increment 8 is inhibitted. |
