| 摘要 |
PURPOSE:To realize plural high speed logical computers by modifying an address at a prescribed level with a constant fed to the operating system. CONSTITUTION:When a logical address is set to an LAR4 and the computer is in the address converting mode, the computer is subject to address conversion from a conventional address converting device 1 and the address is outputted to a data line 17 as a real address. Furthermore, when the computer is in the non- address converting mode, the logical address is fed to a logical circuit 3 as it is. P and -T signals of a register 2 representing the operating state of a central processing unit are fed to the circuit 3, and when P=1, the logical address is outputted to a data line 18 and when P=0, the logical address is outputted to a line 19. Furthermore, the output of the line 18 is modified by a set value alpha of a register 13 by an adder 14 of an additional address converting device 18, and after the result is added to the output of the lines 17, 19 and a storage address register 10; the result is led to a main storage device 11. |
