发明名称 ERROR PULSE DETECTING CIRCUIT
摘要 PURPOSE:To detect error pulses on a transmission path without interrupting the service by inputting the output of a violation detecting circuit to a flip-flop circuit through an OR circuit. CONSTITUTION:When OVBOVB codes B and C are inputted to a B6ZS code decoder and the output of an AND circuit 7 becomes level ''1'' as shown in a figure F, this signal is inputted immediately to a substitutive pattern detector 3, and the detector 3 outputs a clear pulse shown in a figure E to clear shift registers 1 and 2. The output of the second bit of the shift register 1 becomes level ''0'', and the output of the AND circuit 7 becomes level ''0''. In this case, since the time when the output of the AND circuit 7 is level ''1'' is shorter than the one-bit width of a regular pulse, an FF12 is not set and pulses of level ''1'' are not outputted from the FF12. However, in case of an error pulse shown by (c) in a figure B, the clear pulse is not outputted, and therefore, the output of the AND circuit 7 is level ''1'' during the time corresponding to one bit, and a pulse shown in a figure G is outputted from the FF12. Thus, the error pulse is detected.
申请公布号 JPS60121854(A) 申请公布日期 1985.06.29
申请号 JP19830229409 申请日期 1983.12.05
申请人 FUJITSU KK 发明人 FURUKAWA TAKAHIRO;AOKI SHINICHI;ITOU ETSUKO
分类号 H03M13/00;H04L25/49 主分类号 H03M13/00
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