发明名称 CLOCK PULSE GENERATING CIRCUIT
摘要 PURPOSE:To attain IC-implementation easily by performing processing completely digitally by a device which samples data with clock pulses without using any analog filter. CONSTITUTION:When a signal is supplied to a terminal A and the contents of a latch circuit 5 is <=6, ''1'' appears at a terminal P1 of a decision circuit 7 and the contents of a counting circuit 13 are counted up by one. Its contents are converted into an analog voltage and the output frequency of a voltage-controlled oscillator 15 increases. When the contents of the latch circuit 5 are >=23, ''1'' appears at an output terminal P2 of the decision circuit 7 and the output frequency of the voltage-controlled oscillator 15 decreases. When data is ''1'', a circuit makes a similar discrimination and the output frequency of the voltage- controlled oscillator 15 is converged on a normal value. Thus, clock pulses are obtained from the output of a flip-flop circuit 16 to sample the data.
申请公布号 JPS60121844(A) 申请公布日期 1985.06.29
申请号 JP19830229287 申请日期 1983.12.05
申请人 SEIKOUSHIYA:KK 发明人 YAMADA KUNIO;MORIYA NAKANOBU;TANI HIDEO;YOSHIDA SHINJI
分类号 H04L7/033 主分类号 H04L7/033
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