| 摘要 |
PURPOSE:To generate a one-shot signal securely by providing an RS latch which delays a necessary frequency signal and an RS latch which decides on the pulse width of the one-shot signal. CONSTITUTION:Flip-flops 12-15 constitute a frequency dividing circuit and a signal R1 leads a signal S1 by the time corresponding to the total delay of the FFs, so the 1st RS latch 3 operates securely to output a signal S2 generated by delaying the negative edge of the signal S1 by the pulse width of the signal R1; and the signals S2 and R2 are passed through the 2nd RS latch 4 to output a signal T2. Then, the signal S1 and signal T2 are ANDed by an AND gate 5 to obtain a signal P2 which is in phase and has the same time width with the signal R2, and the influence of wiring delay due to electrostatic capacity is prevented to prevent the generation of a whisker-shaped noise. |
