发明名称 FORMING PROCESS OF ELEMENT ISOLATING REGION
摘要 PURPOSE:To flatten buried layers while simplifying the production process by a method wherein grooves with width not exceeding specified value are formed on a semiconductor substrate to form oxide films inside these grooves filling their internal peripheral side with burying material. CONSTITUTION:N<+> type buried layers 2 are formed in a P type semiconductor substrate 1 and the N type epitaxial layers 4 are formed to form P<+> type regions 3 for leveling up the semiconductor 1. Firstly thick SiO2 films 5 are formed by means of selective oxidizing technology. Secondly Si3N4 films 11 and poly Si 12 deposited to form a pattern leveling resists 13 only on the parts to be formed into grooves. Thirdly the pattern is implanted with B utilizing the resists 13 as masks. Fourthly the resists 13 are removed to diffused B. Fifthly the concentration regions of Si 12 specified by the size not exceeding around 1mum are formed to open the Si 12 by the differential etching process forming deep grooves starting from the openings. Sixthly P<+> regions 16 are formed at the bottoms of the grooves. Seventhly the grooves are oxidized to form oxide films 17 filling in the space exceeding half of the groove width. Finally the grooves may be filled with poly Si 15.
申请公布号 JPS60119744(A) 申请公布日期 1985.06.27
申请号 JP19830226811 申请日期 1983.12.02
申请人 HITACHI SEISAKUSHO KK 发明人 OKADA DAISUKE;WATANABE KUNIHIKO;UCHIDA AKIHISA;TAKAKURA TOSHIHIKO
分类号 H01L21/76;H01L21/331;H01L21/762;H01L29/73;H01L29/732 主分类号 H01L21/76
代理机构 代理人
主权项
地址