| 摘要 |
PURPOSE:To realize high-speed bus access and error retry, by providing an error retrying circuit which controls answer signals (reply) to a microprocessor and control signals to the outside by means of the output of an error detecting circuit. CONSTITUTION:When a control signal is outputted from a microprocessor 8, a reply signal 10a is given to an error and reply detecting circuit 11. Then a control signal 12a and change-over signal 12b are given from an error retry controlling circuit 12 to a control signal change-over circuit 9 based on a error detect signal 11a. As a result, the error retry control signal 12a is given to an object 10 to be accessed as an external control signal 9a instead of a control signal 8a. By switching the control signal changeover circuit 9 to the microprocessor 8 side thereafter, retry of bus access is performed. |
