| 摘要 |
PURPOSE:To sharply shorten data transferring time when the content of one memory element is transferred to another memory element, by simultaneously performing the memory reading-out cycle and memory writing cycle. CONSTITUTION:When a memory MO reading-out signal S200 is activated, a chip select signal S10 is also activated through AND gates G40 and G44. At this time, a memory M1 writing signal is simultaneously activated and another chip select signal S11 is also activated. Then a direct reading-out/reading-in selecting signal S21 is set to the writing mode by means of the output of an AND gate 43. Under this condition, the content of an address corresponding to the address designated by an address signal S3 is read out from the memory element MO and outputted onto a data signal S4. At the same time, the data signal S4 is outputted to an address corresponding to the designated address of the memory element M1 and the data of the memory element MO are written. |
