发明名称
摘要 <p>PURPOSE:To easily tranfer data from an external device, and also to execute an interruption response at a high speed, by constituting so that transfer data in the regular mode and refeence data in the interruption mode can be transferred to the side of a microprocessor. CONSTITUTION:A control word is set to a programmable peripheral interface PPI 5 from a master processor 1. In case when the processor 1 tranfers data to an external device 4, a device number is outputted to an address bus, transfer data is sent out to a data bus, and a data write signal WR is supplied to the PPI 5. The transfer data is stored in the PPI 5, the device 4 reads this data by the interruption response processing, and one data transfer ends. In case when the device 4 executes interrption to the processor 1 side, the device 4 sends out reference data to an output terminal of the data bus, the PPI 5 stores it. The processor 1 reads this reference data by the interruption response, and executes the processing corresponding to contents of an interruption request in accordance with said reference data.</p>
申请公布号 JPS6027058(B2) 申请公布日期 1985.06.27
申请号 JP19810024758 申请日期 1981.02.20
申请人 NIPPON DENKI HOOMU EREKUTORONIKUSU KK 发明人 IWAMI TOMOYUKI
分类号 G06F9/48;G06F13/24;G06F15/78 主分类号 G06F9/48
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