| 摘要 |
A video raster display system having a dedicated display address generator is provided. In addition to a microprocessor contained within the video display system providing addresses to a memory the display address generator also generates addresses. The display address generator has a logic unit having a first and a second bus as inputs. A first plurality of registers, some of which are controllably coupled to said first bus and some of which are controllably coupled to said second bus, receives inputs from the microprocessor. A second plurality of registers, some of which are controllably coupled to said first bus and some of which are controllably coupled to said second bus, receives inputs from a video data generator. A third plurality of registers, some of which are controllably coupled to said first bus and some of which are controllably coupled to said second bus, receives the output from the logic unit to controllably provide this output to the logic unit for subsequent operations. |
